A compressive stress or tensile stress can be applied to some types of transistors to increase their performance. For standard orientation Si wafers, the performance of a p-type field effect transistor (pFET) improves when a longitudinal (in the direction of current flow) compressive stress is applied to the channel region. On the other hand, the performance of an n-type field effect transistor (nFET) improves when a longitudinal tensile stress is applied to the channel region. Additionally, for heterostructures comprising different channel materials on an underlying structure, it is favorable to have a quantum barrier between the channel material and underlying structure to help confine carriers to the channel and thus reduce off-state leakage. When nFET devices and pFET devices are used together in a complementary metal oxide semiconductor (CMOS) structure, it is desirable to apply the appropriate type of stress for each device and to achieve the appropriate quantum barrier offset.